Demonstration of Fully Functional 64-kb Josephson/CMOS Hybrid Memory

We have been developing Josephson/CMOS hybrid memories, where decoders and memory cell arrays are composed of CMOS devices and bit-line current sensors are made by Josephson circuits. In our previous study we reported a fully functional 64-kb CMOS static RAM for the hybrid memory, which includes CMOS differential amplifiers with 40-mV voltage inputs. In this paper we demonstrate a fully functional 64-kb Josephson/CMOS hybrid memory, which is composed SFQ input/output circuits using the AIST Nb standard process and a CMOS static RAM using the Rohm 180 nm CMOS process. All input data, are inputs to the hybrid memory as SFQ signals in the system. The total access time was measured to be about 1.69 ns.