The Demonstration of Gate Dielectric -fuse 4kb OTP Memory Feasible for Embedded Applications in High -k Metal-gate CMOS Generations and Beyond

被引：0
|
作者：
Hsieh, E. R. [1 ,2 ]
Chang, C. W. [1 ]
Chuang, C. C. [1 ]
Chen, H. W. [1 ,3 ]
Chung, Steve S. [1 ]
机构：
[1] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu, Taiwan
[2] Stanford Univ, Dept Elect Engn, Stanford, CA 94305 USA
[3] United Microelect Corp UMC, Hsinchu, Taiwan
来源：
2019 SYMPOSIUM ON VLSI CIRCUITS | 2019年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A 4kb macro of One Time Programming (OTP) memory, implemented by a new breakdown, named dielectric fuse (dFuse) breakdown, has been realized on a foundry pure logic 28nm HKMG CMOS platform. The feature size of a unit cell is 1.5T per cell with 7.5F2. The experimental results show that dFuse macro exhibits high programming (PGM) speed of 100ns at 4V, read time smaller than lOns at 0.75V, and excellent data retention under one -month baking at 150 C. More importantly, the program voltage is weakly dependent on the environmental temperature, suitable for automotive applications. This OTP is also expected to be scalable to advanced node such as FinFET and provides an ideal and reliable solution for the storage purpose in loT and 5G era.
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页码：C208 / C209
页数：2
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