Design techniques for Gb/s of CMOS SCL circuits applications

被引：0

作者：

Lu, JH ^{[1
]}

Tian, L ^{[1
]}

Chen, HT ^{[1
]}

Xie, TT ^{[1
]}

Chen, ZH ^{[1
]}

Wang, ZG ^{[1
]}

机构：

[1] SE Univ, Inst RF&OE ICs, Radio Engn Dept, Nanjing 210096, Peoples R China

来源：

2001 4TH INTERNATIONAL CONFERENCE ON ASIC PROCEEDINGS | 2001年

关键词：

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents the design techniques of Gb/s CMOS SCL circuits. Basic SCL functional cells including a 2:1 multiplexer, a D-latch, and XOR/NXOR, AND/NAND, OR/NOR gates are described in detail. Simulations show that a SCL static frequency divider can operate faster than a CMOS static logic one. Experimental results of an SCL 1:4 static frequency divider and an SCL 4:1 multiplexer both in 0.35mum CMOS technology prove that SCL circuits can be used in Gb/s applications.

引用

页码：559 / 562

页数：4

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