共 50 条
- [32] On-chip communication architecture for OC-768 network processors 38TH DESIGN AUTOMATION CONFERENCE PROCEEDINGS 2001, 2001, : 678 - 683
- [33] ReliNoC: A Reliable Network for Priority-Based On-Chip Communication 2011 DESIGN, AUTOMATION & TEST IN EUROPE (DATE), 2011, : 667 - 672
- [34] Power analysis of system-level on-chip communication architectures INTERNATIONAL CONFERENCE ON HARDWARE/SOFTWARE CODESIGN AND SYSTEM SYNTHESIS, 2004, : 236 - 241
- [35] Power-Efficient Calibration and Reconfiguration for On-Chip Optical Communication DESIGN, AUTOMATION & TEST IN EUROPE (DATE 2012), 2012, : 1501 - 1506
- [36] A low latency and low power indirect topology for on-chip communication PLOS ONE, 2019, 14 (10):
- [37] Delay Optimization of Center Network Cache and Performance Simulation of On-chip Network Communication PROCEEDINGS OF THE 2015 INTERNATIONAL CONFERENCE ON AUTOMATION, MECHANICAL CONTROL AND COMPUTATIONAL ENGINEERING, 2015, 124 : 876 - 881
- [38] Integrating adaptive on-chip storage structures for reduced dynamic power 2002 INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, PROCEEDINGS, 2002, : 141 - 152
- [39] A Laser Power Management Method for On-Chip Photonic Interconnect 2016 SEVENTH INTERNATIONAL GREEN AND SUSTAINABLE COMPUTING CONFERENCE (IGSC), 2016,
- [40] Evaluating Design Tradeoffs in On-Chip Power Management for CMPs ISLPED'07: PROCEEDINGS OF THE 2007 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, 2007, : 44 - 49