A Pipelined Market Data Processing Architecture to Overcome Financial Data Dependency

The ability of ultra-low latency to process market data feed is the premise and foundation for a today's trading system to grab the instant trading profits. The market data feed containing up-to-date information on market changes is multicasted real-timely from financial exchanges to market participants, usually in the form of financial information exchange (FIX) Adapted for STreaming (FAST) protocol. FAST is a differential compression protocol which significantly reduces the bandwidth requirement to transmit market data. However, it also increases the complexity and latency of market data processing. This paper describes a customized architecture for ultra-low latency of market-data processing. Firstly, we propose a bus-based architecture of market-data decoding on Field Programmable Gate Array (FPGA). Our design is a loose-coupled and scalable architecture which is easy to adapt to different FAST templates by connecting different decoders to the main bus. Then we further exploit a dedicated pipelined design to improve the architecture. The pipelined architecture decompresses multiple messages in parallel, overcoming the challenge of data dependency between consecutive differential encoded (FAST) messages. Finally, we implement two prototypes in RTL code and evaluate them on a Xilinx Kintex-7 FPGA. Real test results show that 1) the pipelined processor gains 180% speedup compared with the non-pipelined processor; 2) it achieves an ultra-low decoding latency of 307 ns per message, which is 2 orders of magnitude faster than the software solution.