Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications

被引:6
|
作者
Pasricha, Sudeep [1 ]
Dutt, Nikil [2 ]
Kurdahi, Fadi J. [2 ]
机构
[1] Colorado State Univ, Ft Collins, CO 80523 USA
[2] Univ Calif Irvine, Irvine, CA USA
来源
22ND INTERNATIONAL CONFERENCE ON VLSI DESIGN HELD JOINTLY WITH 8TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS | 2009年
关键词
D O I
10.1109/VLSI.Design.2009.84
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The current paradigm of using Cu interconnects for on-chip global communication is rapidly becoming a serious performance bottleneck in ultra-deep submicron (UDSM) technologies. Carbon nanotube (CNT) based interconnects have been proposed as an alternative, because of their remarkable conductive, mechanical and thermal properties. In this paper, we investigate the system level performance of single-walled CNT (SWCNT) bundles, and mixed SWCNT/multi-walled CNT (MWCNT) bundles. Detailed RLC equivalent circuit models for conventional Cu and CNT bundle interconnects are described and used to determine propagation delays. These models are then incorporated into a system-level environment to estimate the impact of using CNT bundle global interconnects on the overall performance of several multi-core chip multiprocessor (CMP) applications. Our results indicate that the CNT bundle alternatives have a slight performance advantage over Cu global interconnects. With further improvements in CNT fabrication technology, we show how CNT bundle-based interconnects can significantly outperfom Cu interconnects.
引用
收藏
页码:499 / +
页数:2
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