VPN acceleration using reconfigurable System-on-Chip technology

被引:0
|
作者
Wee, C. M. [1 ]
Sutton, P. R. [1 ]
Bergmann, N. W. [1 ]
Williams, J. A. [1 ]
机构
[1] Univ Queensland, Sch Informat Technol & Elect Engn, Brisbane, Qld 4072, Australia
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper presents a network architecture that can be implemented on a reconfigurable System-on-Chip (rSoC) that will accelerate the operation of Virtual Private Networks (VPNs). With a small and efficient 3DES-CBC core coupled the flexibility of the rSoC and a network architecture that can scale as needed, this can be an effective solution to the current real world requirement for a flexible and affordable VPN platform.
引用
收藏
页码:281 / +
页数:2
相关论文
共 50 条
  • [21] System-on-chip test scheduling with reconfigurable core wrappers
    Larsson, E
    Fujiwara, H
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2006, 14 (03) : 305 - 309
  • [22] Non-Rectangular Reconfigurable Cores for System-on-Chip
    Alves, Pedro
    Ferreira, Joao Canas
    VLSI CIRCUITS AND SYSTEMS IV, 2009, 7363
  • [23] RtrASSoc - An adaptable superscalar reconfigurable system-on-chip the simulator
    Silva, JL
    Costa, RM
    Jorge, GHR
    3RD IEEE INTERNATIONAL WORKSHOP ON SYSTEM-ON-CHIP FOR REAL-TIME APPLICATIONS, PROCEEDINGS, 2003, : 196 - 200
  • [24] Multi stream cipher architecture for reconfigurable system-on-chip
    Wee, C. M.
    Sutton, P. R.
    Bergmann, N. W.
    Williams, J. A.
    2006 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, 2006, : 769 - 772
  • [25] A Scalable System-on-Chip Acceleration for Deep Neural Networks
    Shehzad, Faisal
    Rashid, Muhammad
    Sinky, Mohammed H.
    Alotaibi, Saud S.
    Zia, Muhammad Yousuf Irfan
    IEEE ACCESS, 2021, 9 : 95412 - 95426
  • [26] System level modelling of reconfigurable FFT architecture for system-on-chip design
    Ahmadinia, Ali
    Ahmad, Balal
    Arslan, Tughrul
    NASA/ESA CONFERENCE ON ADAPTIVE HARDWARE AND SYSTEMS, PROCEEDINGS, 2007, : 169 - +
  • [27] A system-on-chip dynamically reconfigurable FPGA platform for matrix inversion
    Jianwen, Luo
    Chuen, Jong Ching
    2007 INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS, VOLS 1 AND 2, 2007, : 465 - 468
  • [28] A domain specific reconfigurable Viterbi fabric for system-on-chip applications
    Zhan, Cheng
    Arslan, Tughrul
    Khawam, Sami
    Lindsay, Iain
    ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2005, : 916 - 919
  • [29] UTSi® CMOS technology for system-on-chip solution
    Megahed, M
    Burgener, M
    Cable, J
    Staab, D
    Reedy, R
    1998 TOPICAL MEETING ON SILICON MONOLITHIC INTEGRATED CIRCUITS IN RF SYSTEMS: DIGEST OF PAPERS, 1998, : 94 - 99
  • [30] A reconfigurable system-on-chip architecture for medical imaging: Preliminary results
    Zhang, Hui
    Gu, Zi
    Xia, Mingxin
    Tang, Zhiwei
    Hu, Guangshu
    2005 27TH ANNUAL INTERNATIONAL CONFERENCE OF THE IEEE ENGINEERING IN MEDICINE AND BIOLOGY SOCIETY, VOLS 1-7, 2005, : 1747 - 1749