A Reconfigurable Architecture for 1-D and 2-D Discrete Wavelet Transform

被引:5
|
作者
Sun, Qing [1 ]
Jiang, Jiang [1 ]
Zhu, Yongxin [1 ]
Fu, Yuzhuo [1 ]
机构
[1] Shanghai Jiao Tong Univ, Sch Microelect, Shanghai 200030, Peoples R China
关键词
DWT; reconfigurable; FPGA implementation; pipeline architecture; high flexibility; VLSI ARCHITECTURE;
D O I
10.1109/FCCM.2013.23
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, we propose a novel architecture for DWT that can be reconfigured to be adapted to different kinds of filter banks and different sizes of inputs. High flexibility and generality are achieved by using the MAC loop based filter(MLBF). Classic methods, such as polyphase structure and fragment-based sample consumption, are used to enhance the parallelism of the system. The architecture can be reconfigured to 3 modes to deal with 1-D or 2-D DWT with different bandwidth and throughput requirements.
引用
收藏
页码:81 / 84
页数:4
相关论文
共 50 条
  • [41] A novel FPGA architecture of a 2-D Wavelet Transform
    Palero, RJC
    Girones, RG
    Cortes, AS
    JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2006, 42 (03): : 273 - 284
  • [42] A Novel FPGA Architecture of a 2-D Wavelet Transform
    Ricardo José Colom Palero
    Rafael Gadea Gironés
    Angel Sebastia Cortes
    Journal of VLSI signal processing systems for signal, image and video technology, 2006, 42 : 273 - 284
  • [43] A Unified FPGA-Based System Architecture for 2-D Discrete Wavelet Transform
    Ishmael Sameen
    Yoong Choon Chang
    Mow Song Ng
    Bok-Min Goi
    Chee-Pun Ooi
    Journal of Signal Processing Systems, 2013, 71 : 123 - 142
  • [44] A Unified FPGA-Based System Architecture for 2-D Discrete Wavelet Transform
    Sameen, Ishmael
    Chang, Yoong Choon
    Mow Song Ng
    Goi, Bok-Min
    Ooi, Chee-Pun
    JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2013, 71 (02): : 123 - 142
  • [45] A Fast Parallel VLSI Architecture for Lifting Based 2-D Discrete Wavelet Transform
    Kim, Jong Woog
    Chong, Jong Wha
    IECON 2004: 30TH ANNUAL CONFERENCE OF IEEE INDUSTRIAL ELECTRONICS SOCIETY, VOL 2, 2004, : 1258 - 1262
  • [46] A Pipeline VLSI Architecture for High-Speed Computation of the 1-D Discrete Wavelet Transform
    Zhang, Chengjun
    Wang, Chunyan
    Ahmad, M. Omair
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2010, 57 (10) : 2729 - 2740
  • [47] Efficient VLSI Architecture for Implementation of 1-D Discrete Wavelet Transform Based on Distributed Arithmetic
    Mahajan, Anurag
    Mohanty, Basant K.
    PROCEEDINGS OF THE 2010 IEEE ASIA PACIFIC CONFERENCE ON CIRCUIT AND SYSTEM (APCCAS), 2010, : 1195 - 1198
  • [48] Method of fast 1-D paired transforms for computing the 2-D discrete hadamard transform
    Grigoryan, AM
    Agaian, SS
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 2000, 47 (10): : 1098 - 1104
  • [49] A "double-face" bit-serial architecture for the 1-D discrete wavelet transform
    Marino, F
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 2000, 47 (01): : 65 - 71
  • [50] Method of fast 1-D paired transforms for computing the 2-D discrete Hadamard transform
    Grigoryan, AM
    Agaian, SS
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 2000, 47 (12): : 1399 - 1404