VHDL description for SDH system simulation and circuit synthesis

This paper presents a specific system architecture that was developed to define a set of circuits required to build a complete SDH (Synchronous Digital Hierarchy) system interfacing respectively with 2 Mbits/s, 34 Mbits/s and 139 Mbits/s PDH (Plesiochronous Digital Hierarchy) networks. The design methodology is based on high level description of complete SDH nodes in order to meet different objectives that could be defined at the project level. On one hand, the System Engineer has the capability to easily build models from precise specifications and execute functional simulation at the system level. On the other hand, the design engineer can adapt the VHDL code, eventually modify the partitioning and choose the circuits architecture in order to obtain the best hardware implementation.