Silicon debug: Avoid needless respins

For large and complex SoCs, existing techniques such as simulation, formal verification, static timing analysis and signal integrity analysis cannot guarantee silicon to be 100% functionally correct first time. Each remaining design error after first tape-out must be found as quickly as possible. Philips developed a structured approach to debug multiple-clock SoC designs in prototype application boards or on digital IC testers. The approach consists of an on-chip debug infrastructure and supporting debugger software. The debugger software interacts with the on-chip infrastructure to make the chip state observable and controllable. In this paper we describe our silicon debug approach and we include results on the application of our debugging system to two large system chips: the Philips Nexperia(TM) Home Entertainment Engine and the first generation Philips Nexperia(TM) CODEC SoC.