Process challenges in CMOS FEOL for 32nm node

被引：0

作者：

Wang, Guohua ^{[1
]}

Wu, Hanming ^{[1
]}

机构：

[1] SMIC, Beijing 100176, Peoples R China

来源：

2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4 | 2008年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

With the navigation of ITRS, 32nm technology node will be introduced around 2009.(1) Scaling of CMOS devices from 45nm to 32nm node has come across significant barriers. In order to overcome these pitch-scaling induced barriers, it is demanded to integrate the most advanced process technologies into the product manufacturing. This paper will review and discuss new technology applications, which would be potentially integrated into the front end of line (FEOL) of 32nm node. Some examples are discussed in the following areas: double patteming,(2) direct silicon bonding (DSB), hybrid orientation substrate technology,(3) Metal/High-K (MHK) gate stacks, stress technologies and ultra-shallow junction (USJ).

引用

页码：1126 / 1129

页数：4

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