Highly-parallel decoding architectures for convolutional turbo codes

被引：9

作者：

He, Zhiyong ^{[1
]}

Fortier, Paul ^{[1
]}

Roy, Sebastien ^{[1
]}

机构：

[1] Univ Laval, Dept Elect & Comp Engn, Quebec City, PQ G1K 7P4, Canada

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2006年 / 14卷 / 10期

基金：

加拿大自然科学与工程研究理事会;

关键词：

decoder; interleaver; parallel architecture; turbo code;

D O I：

10.1109/TVLSI.2006.884172

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Highly parallel decoders for convolutional turbo codes have been studied by proposing two parallel decoding architectures and a design approach of parallel interleavers. To solve the memory conflict problem of extrinsic information in a parallel decoder, a block-like approach in which data is written row-by-row and READ diagonal-wise is proposed for designing collision-free parallel interleavers. Furthermore, a warm-up-free parallel sliding window architecture is proposed for long turbo codes to maximize the decoding speeds of parallel decoders. The proposed architecture increases decoding speed by 6%-34% at a cost of a storage increase of 1% for an eight-parallel decoder. For short turbo codes (e.g., length of 512 bits), a warm-up-free parallel window architecture is proposed to double the speed at the cost of a hardware increase of 12%.

引用

页码：1147 / 1151

页数：5

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