A Soft RISC-V Processor IP with Highperformance and Low-resource consumption for FPGA

Compared with hardcore processors, adding softcore processors can help FPGA to improve reliability. Many existing soft processors only aim at minimizing FPGA resources consumption or achieving high performance. However, a high-performance processor with low-resource consumption is demanded in implementing the hardware accelerator. To achieve this goal, a 32-bit soft processor based on the RISC-V instruction is proposed in this paper. The proposed processor supports RV32IM and configurable pipelining. A hierarchical decoding architecture is presented to reduce the redundancy in the decoding stage, which can reduce resource consumption. A performance optimization scheme is proposed which is used in the execution unit aiming at improving operating frequency and instructions per cycle (IPC). The operating frequency is improved by shortening the critical path and IPC is improved by reducing the stall cycles. The proposed processor is implemented on a Xilinx Zedboard and compared with the commercial soft processor-MicroBlaze. The performance of the proposed processor is 3.75 times higher than that of MicroBlaze with resource consumption increasing only 7%.