New Silicon Hard Mask Material Development for sub 5 nm Node

被引:3
|
作者
Seko, Tomoaki [1 ]
Kasai, Tatsuya [1 ]
Serizawa, Ryuuichi [1 ]
Dei, Satoshi [2 ]
Sakai, Tatsuya [1 ]
机构
[1] JSR Corp, Semicond Mat Lab, Fine Elect Res Labs, 100 Kawajiri Cho, Yokaichi, Mie 5108552, Japan
[2] JSR Micro NV, Technol Laan 8, B-3001 Leuven, Belgium
关键词
Si-C; Tri-layer process; SOG; Si-HM; SOC; EUV Lithography; Gap-Fill;
D O I
10.1117/12.2518785
中图分类号
O43 [光学];
学科分类号
070207 ; 0803 ;
摘要
New spin-on silicon hard mask (Si-HM) material containing Si-C structure in main chain was developed to meet EUV lithography performance, etch requirements and non-lithography patterning applications at sub 5 nm node. New Si-HM material can be used as an alternative to traditional polysiloxane Si-HM. It showed 2.5X high resistance for oxygen etching compared to polysiloxane Si-HM structure due to low electronegative gap and higher silicon content. It can be chemically modified with various functional units, and photoresist adhesion control would be expected to improve. We also observed sensitivity improvement from EUV lithography tri-layer patterning process including new Si-HM. Wet strip-ability with DHF and refractive index at 193 nm were changed significantly for this new Si-HM before and after UV irradiation under air. It also showed excellent gap-fill performance at narrow pattern dimensions on our patterned wafers.
引用
收藏
页数:7
相关论文
共 50 条
  • [31] Development of silicon containing resists for sub-100nm lithography
    Hatakeyama, J
    Takeda, T
    Nakashima, M
    Kinsho, T
    Kawai, Y
    Ishihara, T
    JOURNAL OF PHOTOPOLYMER SCIENCE AND TECHNOLOGY, 2004, 17 (04) : 519 - 525
  • [32] High Resolution Patterning for Sub 30 nm Technology Nodes Using a Ceramic Based Dual Hard Mask
    Paul, J.
    Rudolph, M.
    Riedel, S.
    Thrun, X.
    Beyer, V.
    Wege, S.
    Hohle, C.
    PLASMA PROCESSING 19, 2013, 50 (46): : 21 - 31
  • [33] Integrated process of photoresist trimming and dielectric hard mask etching for sub-50 nm gate patterning
    Bliznetsov, V
    Kumar, R
    Lin, HZ
    Ang, KW
    Yoo, WJ
    Du, AY
    THIN SOLID FILMS, 2006, 504 (1-2) : 117 - 120
  • [34] Three-dimensional mask effect approximate modeling for sub-50 nm node device OPC
    Suh, Sungsoo
    Lee, SukJoo
    Back, Kyoung-yoon
    Lee, Sook
    Kim, Youngchang
    Kim, Sangwook
    Chun, Yong-Jin
    DESIGN FOR MANUFACTURABILITY THROUGH DESIGN-PROCESS INTEGRATION, 2007, 6521
  • [35] Fabrication of sub-10 nm silicon tips: A new approach
    Huq, SE
    Chen, L
    Prewett, PD
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 1995, 13 (06): : 2718 - 2721
  • [36] New etch challenges for the 65-nm technology node Low-k integration using An enhanced Trench First Hard Mask architecture
    Posseme, N.
    Maurice, C.
    Brun, Ph.
    Ollier, E.
    Guillermet, M.
    Verove, C.
    Berger, T.
    Fox, R.
    Hinsinger, O.
    PROCEEDINGS OF THE IEEE 2006 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2006, : 36 - +
  • [37] Development and Characterization of Advanced Phase Shift Mask Blanks for 14nm node and beyond
    Kim, Chang-Jun
    Jang, Kyu-Jin
    Choi, Min-Ki
    Yang, Chul-Kyu
    Lee, Jae-Chul
    Lee, Jong-Keun
    Kang, Byung-Sun
    Lee, Jong-Hwa
    Shin, Cheol
    Nam, Kee-Soo
    PHOTOMASK TECHNOLOGY 2014, 2014, 9235
  • [38] Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub 5-nm Node SoC Application
    Jeong, Jinsu
    Yoon, Jun-Sik
    Lee, Seunghwan
    Baek, Rock-Hyun
    IEEE ACCESS, 2020, 8 : 35873 - 35881
  • [39] Simulation and characterization of silicon oxynitrofluoride film as a phase shift mask material for 157 nm optical lithography
    Kim, S
    Choi, E
    Kim, H
    Kim, J
    No, K
    OPTICAL MICROLITHOGRAPHY XV, PTS 1 AND 2, 2002, 4691 : 1696 - 1702
  • [40] Sub-1-nm-node beyond-silicon materials and devices: Pathways,opportunities and challenges
    Yue Zhang
    NationalScienceOpen, 2023, 2 (04) : 4 - 5