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- [2] An effective BIST scheme for delay testing ISCAS '98 - PROCEEDINGS OF THE 1998 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6, 1998, : A288 - A291
- [3] A BIST scheme for testing a multiple FPGA system 2002 45TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, CONFERENCE PROCEEDINGS, 2002, : 45 - 48
- [4] A Novel BIST Scheme for Low Power Testing PROCEEDINGS 2010 3RD IEEE INTERNATIONAL CONFERENCE ON COMPUTER SCIENCE AND INFORMATION TECHNOLOGY, (ICCSIT 2010), VOL 1, 2010, : 134 - 137
- [5] Noise-Tolerant DAC BIST Scheme Using Integral Calculus Approach IEICE TRANSACTIONS ON ELECTRONICS, 2011, E94C (08): : 1344 - 1347
- [6] A complete BIST scheme for ADC linearity testing 2004: 7TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUITS TECHNOLOGY, VOLS 1- 3, PROCEEDINGS, 2004, : 2051 - 2054
- [7] A low-cost BIST scheme for ADC testing 2005 6TH INTERNATIONAL CONFERENCE ON ASIC PROCEEDINGS, BOOKS 1 AND 2, 2005, : 665 - 668
- [8] A new BIST scheme based on a summing-into-timing-signal principle with self calibration for the DAC 13TH ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2004, : 58 - 61
- [9] A BIST scheme for testing the interconnects of sram-based FPGAs 2002 45TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, CONFERENCE PROCEEDINGS, 2002, : 41 - 44
- [10] A BIST Scheme for Testing and Repair of Multi-Mode Power Switches 2011 IEEE 17TH INTERNATIONAL ON-LINE TESTING SYMPOSIUM (IOLTS), 2011,