BIST scheme for DAC testing

被引:13
|
作者
Chang, SJ [1 ]
Lee, CL [1 ]
Chen, JE [1 ]
机构
[1] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 300, Taiwan
关键词
D O I
10.1049/el:20020530
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A low-cost, built-in self-test (BIST) scheme for a digital-to-analogue converter (DAC) is presented. The basic idea is to convert the DAC output voltages corresponding to different input codes into different oscillation frequencies through a voltage controlled oscillator (VCO), and further transfer these frequencies to different digital codes using a counter. According to the input and output codes, performances of a DAC, such as offset error, gain error, differential nonlinearity (DNL), integral nonlinearity (INL), could be effectively detected by simply using digital circuits rather than complex analogue ones. In addition, the annoying DAC output noise could be naturally filtered out by this BIST method.
引用
收藏
页码:776 / 777
页数:2
相关论文
共 50 条
  • [41] Microarchitectural synthesis for rapid BIST testing
    Orailoglu, A
    Harris, IG
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1997, 16 (06) : 573 - 586
  • [42] A Bist Scheme for Non-Volatile Memories
    Piero Olivo
    Marcello Dalpasso
    Journal of Electronic Testing, 1998, 12 : 139 - 144
  • [43] An efficient controlled LFSR hybrid BIST scheme
    Liu, Tieqiao
    Liu, Peng
    Liu, Yi
    IEICE ELECTRONICS EXPRESS, 2018, 15 (08):
  • [44] BIST scheme for non-volatile memories
    Olivo, Piero
    Dalpasso, Marcello
    Journal of Electronic Testing: Theory and Applications (JETTA), 1998, 12 (1-2): : 139 - 144
  • [45] ADC/DAC Loopback Linearity Testing by DAC Output Offsetting and Scaling
    Huang, Xuan-Lun
    Huang, Jiun-Lang
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2011, 19 (10) : 1765 - 1774
  • [46] A BIST scheme for FPGA interconnect delay faults
    Wang, CC
    Liou, JJ
    Peng, YL
    Huang, CT
    Wu, CW
    23RD IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2005, : 201 - 206
  • [47] A BIST scheme for non-volatile memories
    Olivo, P
    Dalpasso, M
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 1998, 12 (1-2): : 139 - 144
  • [48] DAC TESTING USING MODULATED SIGNALS
    Fexa, Pavel
    Vedral, Josef
    Svatos, Jakub
    METROLOGY AND MEASUREMENT SYSTEMS, 2011, 18 (02) : 283 - 293
  • [49] Using of Pulse Signals for DAC Testing
    Fexa, Pavel
    Vedral, Josef
    2011 INTERNATIONAL CONFERENCE ON APPLIED ELECTRONICS (AE), 2011,
  • [50] DAC TESTING USING IMPULSE SIGNALS
    Vedral, Josef
    Fexa, Pavel
    METROLOGY AND MEASUREMENT SYSTEMS, 2012, 19 (01) : 105 - 114