Recent developments in deca-nanometer vertical MOSFETs

被引：10
|
作者：
Hall, S
Donaghy, D
Buiu, O
Gili, E
Uchino, T
Kunz, VD
de Groot, CH
Ashburn, P
机构：
[1] Univ Liverpool, Dept Elect Engn & Elect, Liverpool L69 3GJ, Merseyside, England
[2] Univ Southampton, Dept Elect & Comp Sci, Southampton SO9 5NH, Hants, England
来源：
MICROELECTRONIC ENGINEERING | 2004年 / 72卷 / 1-4期
关键词：
D O I：
10.1016/j.mee.2003.12.042
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We report simulations and experimental work relating to innovations in the area of ultra short channel vertical transistors. The use of dielectric pockets can mitigate short channel effects of charge sharing and bulk punch-through; thickened oxide regions can minimize parasitic overlap capacitance in source and drain; a narrow band gap, SiGe source can reduce considerably the gain of the parasitic bipolar transistor which is particularly severe in vertical MOSFETs. The work is put into the context of the ITRS roadmap and it is demonstrated that vertical transistors can provide high performance at relaxed lithographic constraints. (C) 2004 Elsevier B.V. All rights reserved.
引用
收藏
页码：230 / 235
页数：6
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