An optimised dynamic bottleneck dispatching policy for semiconductor wafer fabrication

被引：13

作者：

Zhang, Huai ^{[1
]}

Jiang, Zhibin ^{[1
]}

Guo, Chengtao ^{[1
]}

机构：

[1] Shanghai Jiao Tong Univ, Dept Ind Engn & Management, Shanghai 200240, Peoples R China

来源：

INTERNATIONAL JOURNAL OF PRODUCTION RESEARCH | 2009年 / 47卷 / 12期

基金：

中国国家自然科学基金;

关键词：

dynamic bottleneck dispatching (DBD); semiconductor wafer fabrication system (SWFS); response surface methodology (RSM); simulation optimisation; PERFORMANCE EVALUATION; PETRI-NET; SIMULATION; DESIGN;

D O I：

10.1080/00207540701805638

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

A dynamic bottleneck dispatching (DBD) policy is designed in this paper to detect bottlenecks in a timely way and make adaptive dispatching decisions of semiconductor wafer fabrication systems according to the real-time conditions. Control parameters of the proposed DBD algorithm are optimised by response surface methodology (RSM) and desirability functions. Numerical results show that DBD outperforms common scheduling rules such as CR + FIFO, EDD, SRPT, SPT, SPNB and an existing dynamic bottleneck dispatching method.

引用

页码：3333 / 3343

页数：11

共 50 条

[31] Multi criteria dynamic dispatching schema for balancing the load on lithographical tools in wafer fabrication
Pan, CC
Lo, HS
Chang, CC
2002 SEMICONDUCTOR MANUFACTURING TECHNOLOGY WORKSHOP, 2002, : 183 - 186
[32] A New Release Control Policy (WRELM) For Semiconductor Wafer Fabrication Facilities
Chen, Z. B.
Pan, X. W.
Li, L.
Chen, Q. J.
Xu, W. S.
2014 IEEE 11TH INTERNATIONAL CONFERENCE ON NETWORKING, SENSING AND CONTROL (ICNSC), 2014, : 64 - 68
[33] SCHEDULING SEMICONDUCTOR WAFER FABRICATION
WEIN, LM
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 1988, 1 (03) : 115 - 130
[34] A simulation study on dispatching rules in semiconductor wafer fabrication facilities with due date-based objectives
Chiang, Tsung-Che
Fu, Li-Chen
2006 IEEE INTERNATIONAL CONFERENCE ON SYSTEMS, MAN, AND CYBERNETICS, VOLS 1-6, PROCEEDINGS, 2006, : 4660 - +
[35] Production Scheduling of Semiconductor Wafer Fabrication Facilities Using Real-Time Combinatorial Dispatching Rule
Panigrahi, Suraj
Agrahari, Srijeta
Machado, Jose
Manupati, V. K.
INTERNATIONAL CONFERENCE ON RELIABLE SYSTEMS ENGINEERING (ICORSE) - 2021, 2022, 305 : 78 - 90
[36] A dynamic hot lot determination model in a semiconductor wafer fabrication factory
Chang, SH
Yen, PL
Wang, K
INTERNATIONAL JOURNAL OF INDUSTRIAL ENGINEERING-THEORY APPLICATIONS AND PRACTICE, 2005, 12 (02): : 107 - 116
[37] A DBR and ANFIS integrated dynamic scheduling algorithm for semiconductor wafer fabrication
Cao, Zheng-Cai
Peng, Ya-Zhen
Li, Bo
Liu, Min
Tien Tzu Hsueh Pao/Acta Electronica Sinica, 2015, 43 (10): : 2082 - 2087
[38] A survey of dispatching rules for operational control in wafer fabrication
Sarin, Subhash C.
Varadarajan, Amrusha
Wang, Lixin
PRODUCTION PLANNING & CONTROL, 2011, 22 (01) : 4 - 24
[39] DISPATCHING IN AN INTEGRATED-CIRCUIT WAFER FABRICATION LINE
JOHRI, PK
1989 WINTER SIMULATION CONFERENCE PROCEEDINGS, 1989, : 918 - 921
[40] Simulation-based optimization of dispatching rules for semiconductor wafer fabrication system scheduling by the response surface methodology
Zhang, Huai
Jiang, Zhibin
Guo, Chengtao
INTERNATIONAL JOURNAL OF ADVANCED MANUFACTURING TECHNOLOGY, 2009, 41 (1-2): : 110 - 121

← 1 2 3 4 5 →