Design of low-power clock generator synchronized with AC power for adiabatic dynamic CMOS logic

To reduce the power dissipation in conventional CMOS logic and to maintain adiabatic charging and discharging with low power for the adiabatic dynamic CMOS logic (ADCL), the clock signal of logic circuits should be synchronized with the AC power source. In this paper, the low-power clock generator synchronized with the AC power signal is proposed for ADCL system. From the simulation result, summation of power consumption of the designed wave shaping circuit (WSC) and asymmetry duty ratio divider (ADD) was estimated with approximately 1.197 mu W and 58.1 mu W at 3 kHz and 10 MHz, respectively.