VLSI Implementation of a Cryptography-Oriented Reconfigurable Array

The long-word and very long-word addition required in cryptography applications generally requires custom hardware support provided by ASICs or application-specific instructions in ASIPs. As an altemative to these expensive solutions, FPGAs have been used. To reduce the overhead of commercial FPGAs in implementing cryptography, CryptoRA, a cryptographically-oriented reconfigurable array, has recently been proposed. This paper presents a circuit-level implementation of the CryptoRA array which provides the following results: (i) a speed-up of 1.15 x to 2.1 x from the LUT output to a fast-addition carry path, (ii) a speed-up greater than 1.2 x for long-word addition and subtraction, and (iii) these results come at a cost of only an additional 2.5% of a computing tile's silicon area.