A Parallel VLSI Algorithm for a High Throughput Systolic Array VLSI Implementation of Type IV DCT

An new design approach to derive a high throughput systolic array architecture for a prime length type IV discrete cosine transform based on parallel and pipeline processing is presented. This approach is based on a parallel VLSI algorithm that uses a parallel restructuring of type IV DCT. It uses parallel pseudo-circular correlation structures as basic computational forms. The proposed algorithm can be mapped onto two linear systolic arrays with similar length and form that have a small number of I/O channels and low I/O bandwidth that can be efficiently implemented into a VLSI chip. A highly efficient VLSI chip can be thus obtained that has good performances in the architectural topology, processing speed, hardware complexity and I/O costs and outperforms others especially in throughput.