IMPACCT: Methodology and tools for power-aware embedded systems

被引:7
|
作者
Chou, PH [1 ]
Liu, JF [1 ]
Li, DX [1 ]
Bagherzadeh, N [1 ]
机构
[1] Univ Calif Irvine, Dept Elect & Comp Engn, Irvine, CA 92697 USA
关键词
power-aware scheduling; power mode selection; system-level power management;
D O I
10.1023/A:1019730322551
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Power-aware systems are those that must exploit a wide range of power/performance trade-offs in order to adapt to the power availability and application requirements. They require the integration of many novel power management techniques, ranging from voltage scaling to subsystem shutdown. However, those techniques do not always compose synergistically with each other; in fact, they can combine subtractively and often yield counterintuitive, and sometimes incorrect, results in the context of a complete system. This can become a serious problem as more of these power aware systems are being deployed in mission critical applications. To address the problem of technique integration for power-aware embedded systems, we propose a new design tool framework called IMPACCT and the associated design methodology. The system modeling methodology includes application model for capturing timing/power constraints and mode dependencies at the system level. The tool performs power-aware scheduling and mode selection to ensure that all timing/power constraints are satisfied and that all overhead is taken into account. IMPACCT then synthesizes the implementation targeting a symmetric multiprocessor platform. Experimental results show that the increased dynamic range of power/performance settings enabled a Mars rover to achieve significant acceleration while using less energy. More importantly, our tool correctly combines the state-of-the-art techniques at the system level, thereby saving even experienced designers from many pitfalls of system-level power management.
引用
收藏
页码:205 / 232
页数:28
相关论文
共 50 条
  • [21] Fault-tolerant and power-aware scheduling in embedded real-time systems
    Zhu, Ping
    Luo, DongMei
    Chen, Xuhui
    PROCEEDINGS OF THE 2020 INTERNATIONAL CONFERENCE ON COMPUTER, INFORMATION AND TELECOMMUNICATION SYSTEMS (CITS), 2020, : 60 - 64
  • [22] Power-aware scheduling under timing constraints for mission-critical embedded systems
    Liu, JF
    Chou, PH
    Bagherzadeh, N
    Kurdahi, F
    38TH DESIGN AUTOMATION CONFERENCE PROCEEDINGS 2001, 2001, : 840 - 845
  • [23] The Design and Experiments of A SID-Based Power-Aware Simulator for Embedded Multicore Systems
    Lin, Cheng-Yen
    Huang, Chung-Wen
    Kuan, Chi-Bang
    Huang, Shi-Yu
    Lee, Jenq-Kuen
    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2015, 20 (02)
  • [24] A power-aware multi harvester power unit with hydrogen fuel cell for embedded systems in outdoor applications
    Magno, Michele
    Porcarelli, Danilo
    Benini, Luca
    Brunelli, Davide
    2013 INTERNATIONAL GREEN COMPUTING CONFERENCE (IGCC), 2013,
  • [25] Power-Aware Computing Systems on FPGAs: A Survey
    Akguen, Goekhan
    Ali, Muhammad
    Goehringer, Diana
    2021 31ST INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS (FPL 2021), 2021, : 45 - 51
  • [26] Power-Aware Code Restructuring for Embedded Parallel Storing Device
    Xie Bin
    Shi Qingsong
    Tong Liangliang
    Huang Jiangwei
    Wu Xinliang
    Chen Tianzhou
    2008 IEEE INTERNATIONAL CONFERENCE ON PERVASIVE COMPUTING AND COMMUNICATIONS, 2008, : 627 - 632
  • [27] Power-aware speed scaling in multiprocessor systems
    Singh, Pawan
    IET SCIENCE MEASUREMENT & TECHNOLOGY, 2018, 12 (01) : 25 - 32
  • [28] Embedded power-aware cycle by cycle variable speed processor
    Boyer, F. R.
    Epassa, H. G.
    Savaria, Y.
    IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, 2006, 153 (04): : 283 - 290
  • [29] Power-aware test data compression for embedded IP cores
    Badereddine, N.
    Wang, Z.
    Girard, P.
    Chakrabarty, K.
    Virazel, A.
    Pravossoudovitch, S.
    Landrault, C.
    PROCEEDINGS OF THE 15TH ASIAN TEST SYMPOSIUM, 2006, : 5 - +
  • [30] Efficient system-level prototyping of power-aware dynamic memory managers for embedded systems
    Atienza, D
    Mamagkakis, S
    Poletti, F
    Mendias, JM
    Catthoor, F
    Benini, L
    Soudris, D
    INTEGRATION-THE VLSI JOURNAL, 2006, 39 (02) : 113 - 130