3D Memory Chip Stacking by Multi-Layer Self-Assembly Technology

被引：0

作者：

Fukushima, T. ^{[1
,2
]}

Bea, J. ^{[1
,2
]}

Murugesan, M. ^{[1
,2
]}

Son, H. -Y. ^{[3
]}

Sun, M. -S. ^{[3
]}

Byun, K. -Y. ^{[3
]}

Kim, N. -S. ^{[3
]}

Lee, K. -W. ^{[1
,2
]}

Koyanagi, M. ^{[1
,2
]}

机构：

[1] Tohoku Univ, New Ind Creat Hatchery Ctr, Sendai, Miyagi 980, Japan

[2] Tohoku Univ, GINTI, Sendai, Miyagi 980, Japan

[3] SK Hynix, Icheon, South Korea

来源：

2013 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC) | 2013年

关键词：

Self-Assembly; 3D Chip Stack; Memory; TSV; Microbump; INTEGRATION;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Multi-layer 3D chip stacking by a surface-tension-driven self-assembly technique is demonstrated. After multi-layer self-assembly, memory chips having Cu-SnAg mu hump and Cu-TSVs are bonded on a substrate by thermal compression to confirm electrical joining between them. In addition, we investigate the impacts of wetting properties of chip/substrate surfaces, pump shapes, and p,bump layout on alignment accuracies of self-assembly. Good electrical characteristics are obtained from the TSV-mu bump daisy chains in the stacked memory chips.

引用

页数：4

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