Design optimizations of a high performance microprocessor using combinations of Dual-VT allocation and transistor sizing

被引：20

作者：

Tschanz, J ^{[1
]}

Ye, YB ^{[1
]}

Wei, LQ ^{[1
]}

Govindarajulu, V ^{[1
]}

Borkar, N ^{[1
]}

Burns, S ^{[1
]}

Karnik, T ^{[1
]}

Borkar, S ^{[1
]}

De, VV ^{[1
]}

机构：

[1] Intel Labs, Hillsboro, OR USA

来源：

2002 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2002年

关键词：

D O I：

10.1109/VLSIC.2002.1015089

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Joint optimizations of dual-V-T allocation and transistor sizing reduce low-V-T usage by 36%-45% and leakage power by 20%, with minimal impact on total active power and die area. An enhancement of the optimum design allows processor frequency to be increased efficiently during manufacturing.

引用

页码：218 / 219

页数：2

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