Nanoscale FinFETs for low power applications

被引：15

作者：

Rösner, W ^{[1
]}

Landgraf, E ^{[1
]}

Kretz, J ^{[1
]}

Dreeskornfeld, L ^{[1
]}

Schäfer, H ^{[1
]}

Städele, M ^{[1
]}

Schulz, T ^{[1
]}

Hofmann, F ^{[1
]}

Luyken, RJ ^{[1
]}

Specht, M ^{[1
]}

Hartwich, J ^{[1
]}

Pamler, W ^{[1
]}

Risch, L ^{[1
]}

机构：

[1] Infineon Technol AG, Corp Res, D-81730 Munich, Germany

来源：

SOLID-STATE ELECTRONICS | 2004年 / 48卷 / 10-11期

关键词：

double gate; FinFET; low power; MOSFET;

D O I：

10.1016/j.sse.2004.05.019

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

N and p channel FinFETs with fin widths in the range of 15-30 nm and gate lengths down to 20 nm have been processed using e-beam-lithography and nano-etching. The I-On-I-off characteristics of n-channel FinFET devices with (10 0) and (I 10) sidewall orientation made on the same wafer are compared. Low off currents down to I pA/mum and high on-currents were observed and we demonstrate that FinFETs are more suitable than bulk transistors to achieve the requirements for low power applications. (C) 2004 Elsevier Ltd. All rights reserved.

引用

页码：1819 / 1823

页数：5

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