Design of Low Power ECRL based Power Gated 4:2 Compressor

被引:0
|
作者
Malhotra, Naman [1 ]
Mann, Aarushi [1 ]
Pandey, Neeta [1 ]
机构
[1] Delhi Technol Univ, Dept Elect & Commun, Delhi, India
关键词
Compressor; Low Power VLSI; ECRL; Power Gating; Adiabatic Logic;
D O I
10.1109/spin.2019.8711712
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Advent of new age technologies like augmented reality (AR) has made techniques like digital signal processing (DSP), image and speech processing one of the most frequently used and important techniques. Multipliers are the fundamental components of these techniques which depend on extensive multiplications and numerical manipulations. Compressors are a crucial and important unit of multipliers that largely influence the speed and power dissipation of multipliers. This paper proposes a low power ECRL based 4:2 compressors by employing power gating. Two different power gating methodologies have been evaluated and compared, at varying load capacitances, supply voltage and frequency of the power clock signal, using 32nin PTM CMOS technology parameters. The small overhead observed in active state power dissipations is well compensated for by the significant power savings in idle states.
引用
收藏
页码:891 / 895
页数:5
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