共 50 条
- [21] Model Based Pattern Dummy Generation for Logic Devices OPTICAL MICROLITHOGRAPHY XXVII, 2014, 9052
- [22] SAT-Based Fault Coverage Evaluation in the Presence of Unknown Values 2011 DESIGN, AUTOMATION & TEST IN EUROPE (DATE), 2011, : 1303 - 1308
- [23] Efficient BDD-based Fault Simulation in Presence of Unknown Values 2011 20TH ASIAN TEST SYMPOSIUM (ATS), 2011, : 383 - 388
- [24] Symbolic Observation Graph-Based Generation of Test Paths TESTS AND PROOFS, TAP 2023, 2023, 14066 : 127 - 146
- [25] Automated Test Generation on Path-based Symbolic Execution 2014 5TH IEEE INTERNATIONAL CONFERENCE ON SOFTWARE ENGINEERING AND SERVICE SCIENCE (ICSESS), 2014, : 845 - 848
- [26] Automatic Test Pattern Generation for Virtual Hardware Model using Constrained Symbolic Execution 2015 10TH INTERNATIONAL DESIGN & TEST SYMPOSIUM (IDT), 2015, : 149 - 150
- [27] Specification based test sequence generation with propositional logic SOFTWARE TESTING VERIFICATION & RELIABILITY, 2000, 10 (04): : 229 - 248
- [29] Model generation of test logic for macrocell based designs EURO-DAC '96 - EUROPEAN DESIGN AUTOMATION CONFERENCE WITH EURO-VHDL '96 AND EXHIBITION, PROCEEDINGS, 1996, : 456 - 461
- [30] A temporal logic based theory of test coverage and generation TOOLS AND ALGORITHMS FOR THE CONSTRUCTION AND ANAYLSIS OF SYSTEMS, PROCEEDINGS, 2002, 2280 : 327 - 341