Circuit-Level Reliability Simulator for Front-End-of-Line and Middle-of-Line Time-Dependent Dielectric Breakdown in FinFET Technology

被引:0
|
作者
Yang, Kexin [1 ]
Liu, Taizhi [1 ]
Zhang, Rui [1 ]
Milor, Linda [1 ]
机构
[1] Georgia Inst Technol, Sch Elect & Comp Engn, Atlanta, GA 30332 USA
基金
美国国家科学基金会;
关键词
time-dependent dielectric breakdown; lifetime simulator; wearout; frontend-of-line dielectric breakdown; middle-of-line breakdown; digital circuit; microprocessor; reliability;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper presents a lifetime simulator for both Front-End-of-Line (FEOL) time dependent dielectric breakdown (TDDB) and the newly emerging Middle-of-Line (MOL) time dependent dielectric breakdown for FinFET technology. A lifetime assessment flow for digital circuits and microprocessors is proposed for the target wearout mechanisms, and its associated vulnerable feature extraction algorithms are discussed in detail. Our simulator incorporates the detailed electrical stress, temperature, linewidth of each standard cell within the digital circuit and microprocessor. Also, FEOL TDDB and MOL TDDB lifetimes are combined in the calculation of TDDB lifetime. Circuit designers can use the resulting lifetime information to guide and improve their circuits to make them more robust and reliable.
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页数:6
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