Compact Model of a CBRAM Cell in Verilog-A

被引：0

作者：

Reyboz, M. ^{[1
]}

Onkaraiah, S. ^{[1
]}

Palma, G. ^{[1
]}

Vianello, E. ^{[1
]}

Perniola, L. ^{[1
]}

机构：

[1] CEA, LETI, MINATEC Campus,17 Rue Martyrs, F-38054 Grenoble 9, France

来源：

2012 12TH ANNUAL NON-VOLATILE MEMORY TECHNOLOGY SYMPOSIUM | 2012年

关键词：

CBRAM; resistive memory; NV RAM; compact modeling; Verilog-A;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

CBRAMs (Conductive Bridging Random Access Memory) are a kind of Resistive Random Access Memories (RRAMs) fabricated in the BEOL (Back-End-Of-Line). They are a promising breakthrough for including permanent retention mechanisms (non-volatility) in embedded systems at low cost. Thus, they are becoming very interesting for the designers community as well. To use this device to design innovative circuits, a compact model is mandatory. In this paper, we propose a continuous physical compact model, written in Verilog-A. Main advantage of this approach is its robustness compared to macromodel approach. Moreover, our approach provides more flexibility compared to a behavioural model for adding multilevel aspect. The model is calibrated with the characterization results and integrated in Cadence design flow using Eldo simulator.

引用

页码：94 / 97

页数：4

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