1/f Noise in Drain and Gate Current of MOSFETs With High-k Gate Stacks

被引:105
|
作者
Magnone, P. [1 ]
Crupi, F. [1 ]
Giusi, G. [1 ]
Pace, C. [1 ]
Simoen, E. [2 ]
Claeys, C. [2 ,3 ]
Pantisano, L. [2 ]
Maji, D. [4 ]
Rao, V. Ramgopal [4 ]
Srinivasan, P. [5 ]
机构
[1] Univ Calabria, Dipartimento Elettron Informat & Sistemist, I-87036 Cosenza, Italy
[2] Interuniv Microelect Ctr, B-3001 Louvain, Belgium
[3] Katholieke Univ Leuven, Dept Elect Engn, B-3001 Louvain, Belgium
[4] Indian Inst Technol, Dept Elect Engn, Bombay 400076, Maharashtra, India
[5] Texas Instruments Inc, Dallas, TX 75243 USA
关键词
Drain noise; gate noise; high-k dielectric; MOSFET; 1/f noise; LOW-FREQUENCY NOISE; FLICKER NOISE; IMPACT; BEHAVIOR; DIELECTRICS; NMOSFETS; MOBILITY; DEFECTS; PERFORMANCE; TRANSISTORS;
D O I
10.1109/TDMR.2009.2020406
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, we investigate the quality of MOSFET gate stacks where high-k materials are implemented as gate dielectrics. We evaluate both drain- and gate-current noises in order to obtain information about the defect content of the gate stack. We analyze how the overall quality of the gate stack depends on the kind of high-k material, on the interfacial layer thickness, on the kind of gate electrode material, on the strain engineering, and on the substrate type. This comprehensive study allows us to understand which issues need to be addressed in order to achieve improved quality of the gate stack from a 1/f noise point of view.
引用
收藏
页码:180 / 189
页数:10
相关论文
共 50 条
  • [31] Thermally unstable ruthenium oxide gate electrodes in Metal/High-k gate stacks
    Kadoshima, Masaru
    Aminaka, Toshio
    Kurosawa, Etsuo
    Aoyama, Takayuki
    Nara, Yasuo
    Ohji, Yuzuru
    JAPANESE JOURNAL OF APPLIED PHYSICS, 2008, 47 (04) : 2108 - 2111
  • [32] Modeling of direct tunneling current through interfacial oxide and high-K gate stacks
    Zhao, YJ
    White, MH
    SOLID-STATE ELECTRONICS, 2004, 48 (10-11) : 1801 - 1807
  • [33] Metal gate and high-k gate dielectrics for sub 50 nm high performance MOSFETs
    Park, Hokyung
    Hasan, Musarrat
    Jo, Minseok
    Hwang, Hyunsang
    ELECTRONIC MATERIALS LETTERS, 2007, 3 (02) : 75 - 85
  • [34] Contributions of channel gate and overlap gate currents on 1/f gate current noise for thin oxide gate p-MOSFETs
    Martinez, F
    Laigle, A
    Hoffmann, A
    Valenza, M
    Veloso, A
    Jurczak, M
    Noise and Fluctuations, 2005, 780 : 243 - 246
  • [35] Influence of interlayer properties on the characteristics of high-k gate stacks
    Engstrom, O.
    Mitrovic, I. Z.
    Hall, S.
    SOLID-STATE ELECTRONICS, 2012, 75 : 63 - 68
  • [36] Threshold voltage instabilities in high-k gate dielectric stacks
    Zafar, S
    Kumar, A
    Gusev, E
    Cartier, E
    IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2005, 5 (01) : 45 - 64
  • [37] A semi-empirical analytic model for threshold voltage instability in MOSFETs with high-k gate stacks
    何进
    马晨月
    张立宁
    张健
    张兴
    半导体学报, 2009, 30 (08) : 63 - 66
  • [38] Characterization of mixed-signal properties of MOSFETs with high-k (SiON/HfSiON/TaN) gate stacks
    Rittersma, ZM
    Vertregt, M
    Deweerd, W
    van Elshocht, S
    Srinivasan, P
    Simoen, E
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2006, 53 (05) : 1216 - 1225
  • [39] A semi-empirical analytic model for threshold voltage instability in MOSFETs with high-k gate stacks
    He Jin
    Ma Chenyue
    Zhang Lining
    Zhang Jian
    Zhang Xing
    JOURNAL OF SEMICONDUCTORS, 2009, 30 (08)
  • [40] Review of reliability issues in high-k/metal gate stacks
    Degraeve, R.
    Aoulaiche, M.
    Kaczer, B.
    Roussel, Ph.
    Kauerauf, T.
    Sahhaf, S.
    Groeseneken, G.
    IPFA 2008: PROCEEDINGS OF THE 15TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS, 2008, : 239 - +