Thin-layer silicon-on-insulator high-voltage PMOS device and application

被引:0
|
作者
Letavic, T [1 ]
Albu, R [1 ]
Dufort, B [1 ]
Petruzzello, J [1 ]
Simpson, M [1 ]
Mukherjee, S [1 ]
Weijland, I [1 ]
van Zwol, H [1 ]
机构
[1] Philips Res USA, Briarcliff Manor, NY 10510 USA
关键词
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暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We present a thin-layer silicon-on-insulator (SOI) high-voltage PMOS device structure and measured performance characteristics. The all-implanted device structure supports voltage by multi-dimensional depletion from a combination of implanted surface pn junctions and MOS capacitor structures formed with multi-level dielectric deposition and metallization. A graded-doped body region has been optimized for application voltages from 100-600V, and the structure has been evaluated in applications including high-voltage level shifting, low-dissipation bias networks, and high-voltage high-frequency class AB power output stages. The integrated high-voltage PMOS device structure enables low-power, high voltage, and high-speed complimentary circuit topologies to be realized in a thin-layer SOI process flow, improving circuit efficiency and expanding the application base for thin-layer technology.
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页码:73 / 76
页数:4
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