Modelling charge injection in MOS analogue switches using a compact model in a deep submicron technology

被引：5

作者：

Dei, A. ^{[1
]}

Valle, M. ^{[1
]}

机构：

[1] Univ Genoa, Dept Biophys & Elect Engn DIBE, I-16145 Genoa, Italy

来源：

IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS | 2006年 / 153卷 / 03期

关键词：

D O I：

10.1049/ip-cds:20045088

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Charge injection in MOS switches in a deep submicron technology has been analysed. The analysis has been extended to the general case of including the conduction of the MOS transistor in the moderate and weak inversion regions, using a continuous and physical formulation based on the EKV model. SPICE simulations, based on the BSIM3v3 model, which ensures the charge conservation, have demonstrated the validity of our work.

引用

页码：269 / 273

页数：5

共 50 条

[41] Parasitic resistance considerations of using elevate source/drain for deep submicron MOSFET technology
Sun, J
Srivastava, A
Bartholomew, RF
Bellur, K
Osburn, CM
Masnari, NA
Westhoff, R
ULSI SCIENCE AND TECHNOLOGY / 1997: PROCEEDINGS OF THE SIXTH INTERNATIONAL SYMPOSIUM ON ULTRALARGE SCALE INTEGRATION SCIENCE AND TECHNOLOGY, 1997, 1997 (03): : 587 - 597
[42] An effective routing methodology for Gb/s LSIs using deep-submicron technology
Watanabe, T
Ohtomo, Y
Yamakoshi, K
Takei, Y
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 1998, E81A (04): : 677 - 684
[43] Acceleration of semiconductor device simulation using compact charge model
Lee, Kwang-Woon
Hong, Sung-Min
SOLID-STATE ELECTRONICS, 2023, 199
[44] Noise and speed characteristics of test transistors and charge amplifiers designed using a submicron CMOS technology
Santiard, J.C.
Faccio, F.
Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 1996, 380 (1-2): : 350 - 352
[45] Noise and speed characteristics of test transistors and charge amplifiers designed using a submicron CMOS technology
Santiard, JC
Faccio, F
NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT, 1996, 380 (1-2): : 350 - 352
[46] INJECTION CURRENT MODEL OF A MOS DIODE UNDER CHARGE-SHARING MODE READOUT OPERATION
WU, CW
LIN, HH
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1993, 40 (01) : 227 - 229
[47] A viable self-aligned bottom-gate MOS transistor technology for deep submicron 3-D SRAM
Zhang, SD
Chan, ACK
Han, RQ
Huang, R
Liu, XY
Wang, YY
Ko, PK
Chan, MS
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2003, 50 (09) : 1952 - 1960
[48] New screening concept for deep submicron CMOS VLSIs using temperature characteristics of leakage currents in MOS devices
Shimaya, M
1997 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 35TH ANNUAL, 1997, : 49 - 56
[49] Accurate MOS modelling for analog circuit simulation using the EKV model
Bucher, M
Lallement, C
Enz, C
Krummenacher, F
ISCAS 96: 1996 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - CIRCUITS AND SYSTEMS CONNECTING THE WORLD, VOL 4, 1996, : 703 - 706
[50] Algorithms for minimization of charge sharing effects in a hybrid pixel detector taking into account hardware limitations in deep submicron technology
Maj, P.
Baumbaugh, A.
Deptuch, G.
Grybos, P.
Szczygiel, R.
JOURNAL OF INSTRUMENTATION, 2012, 7

← 1 2 3 4 5 →