Area-minimal algorithm for LUT-Based FPGA technology mapping with duplication-free restriction

被引：0

作者：

Kao, CC ^{[1
]}

Lai, YT ^{[1
]}

机构：

[1] Natl Pingtung Inst Commerce, Dept Informat Technol, Pingtung, Taiwan

来源：

ASP-DAC 2004: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE | 2004年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Minimum area is one of the important objectives in technology mapping for lookup table-based FPGAs. It has been proven that the problem is NP-complete. This paper presents a polynomial time algorithm which can run in O(n(3)) time to generate an efficient solution where n is the total number of gates in the circuit. The proposed algorithm partitions the graph representing the given circuit into subgraphs such that the solution can be obtained by merging the subgraph solutions. The greedy technique is then used to find the solution for each subgraph. It is shown that except for some cases the greedy method can find an optimal solution of a given problem. We have tested our algorithm on a set of benchmark examples. The experimental results demonstrate the effectiveness of our algorithm.

引用

页码：719 / 724

页数：6

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