Field Programmable Gate Array Realization of Microprogrammed Controller based Parallel Digital FIR Filter Architecture

This paper presents Field Programmable Gate Array (FPGA) realization of parallel architecture of microprogrammed controller based digital finite impulse response (FIR) filter. Digital FIR filter consists of a datapath and control unit. The datapath unit for the parallel FIR filter is a combination of bunch of registers, multipliers, adders and other digital building blocks. In this paper, we used the microprogrammed controller to control the operation of the datapath unit. The main advantage of the microprogrammed controller is its flexibility in modifying the microprogram stored in ROM based control memory. To demonstrate the proposed technique, we present a case study of third-order FIR filter. The parallel architecture is coded using VHDL based top-down hierarchical design methodology and realized in Spartan-3E FPGA using Xilinx ISE Webpack 12.2. Based on the FPGA implementation results, the maximum operating frequency of the third-order FIR filter is found to be 74.189 MHz and utilizing minimal FPGA resources. This leaves plenty of FPGA resources available for extending the design to realize higher order and high speed FIR filters which are commonly used in video and image processing applications.