Supply voltage glitches effects on CMOS circuits

被引：9

作者：

Djellid-Ouar, Anissa ^{[1
,2
]}

Cathebras, Guy ^{[1
]}

Bancel, Frederic ^{[2
]}

机构：

[1] LIRMM, UMR 5506, 161 Rue Ada, F-34492 Montpellier 5, France

[2] STMicroelect, Smartcard Div, F-13106 Rousset, France

来源：

IEEE DTIS: 2006 INTERNATIONAL CONFERENCE ON DESIGN & TEST OF INTEGRATED SYSTEMS IN NANOSCALE TECHNOLOGY, PROCEEDINGS | 2006年

关键词：

D O I：

10.1109/DTIS.2006.1708651

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Among the attacks applied on secure circuits, fault injection techniques consist in the use of a combination of environmental conditions that induce computational errors in the chip that can leak protected informations. The purpose of our study is to build an accurate model able to describe the behaviour of CMOS circuits in presence of deliberated short supply voltage variations. This behaviour depends strongly on the basic gates (combinational logic, registers...) that make up the circuit. In this paper., we show why D-flip-flop are resistant to power supply glitches occurring between clock transitions and we propose an approach to evaluate the basic elements sensitivities towards faults generated by power glitches. Our aimed model Nvill consequently be dependent on this sensitivity.

引用

页码：257 / 261

页数：5

共 50 条

[1] CMOS translinear circuits for minimum supply voltage
Seevinck, E
Vittoz, EA
du Plessis, M
Joubert, TH
Beetge, W
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 2000, 47 (12): : 1560 - 1564
[2] A Forward Body Bias Generator for Digital CMOS Circuits with Supply Voltage Scaling
Meijer, Maurice
de Gyvez, Jose Pineda
Kup, Ben
van Uden, Bert
Bastiaansen, Peter
Lammers, Marco
Vertregt, Maarten
2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, : 2482 - 2485
[3] THRESHOLD VOLTAGE GENERATION AND SUPPLY-INDEPENDENT BIASING IN CMOS INTEGRATED-CIRCUITS
TSIVIDIS, YP
ULMER, RW
IEE JOURNAL ON ELECTRONIC CIRCUITS AND SYSTEMS, 1979, 3 (01): : 1 - 4
[4] Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations
Alexander, Jins D.
Agrawal, Vishwani D.
2009 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, 2009, : 127 - 132
[5] CMOS circuits with subvolt supply voltages
Stan, MR
IEEE DESIGN & TEST OF COMPUTERS, 2002, 19 (02): : 34 - 43
[6] Analysis of Delay Time in Subthreshold CMOS Circuits Operating at Ultra-Low Supply Voltage
Jung, Seung-Min
Saraya, Takuya
Hiramoto, Toshiro
2014 IEEE SILICON NANOELECTRONICS WORKSHOP (SNW), 2014,
[7] Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage
Nose, K
Chae, S
Sakurai, T
ISLPED '00: PROCEEDINGS OF THE 2000 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, 2000, : 228 - 230
[8] Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage
Nose, Koichi, 2000, IEEE, Piscataway
[9] On the lower bounds of CMOS supply voltage
Schrom, G
Pichler, C
Simlinger, T
Selberherr, S
SOLID-STATE ELECTRONICS, 1996, 39 (04) : 425 - 430
[10] Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits
Filanovsky, IM
Allam, A
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS, 2001, 48 (07): : 876 - 884

← 1 2 3 4 5 →