Supply voltage glitches effects on CMOS circuits

被引：9

作者：

Djellid-Ouar, Anissa ^{[1
,2
]}

Cathebras, Guy ^{[1
]}

Bancel, Frederic ^{[2
]}

机构：

[1] LIRMM, UMR 5506, 161 Rue Ada, F-34492 Montpellier 5, France

[2] STMicroelect, Smartcard Div, F-13106 Rousset, France

来源：

IEEE DTIS: 2006 INTERNATIONAL CONFERENCE ON DESIGN & TEST OF INTEGRATED SYSTEMS IN NANOSCALE TECHNOLOGY, PROCEEDINGS | 2006年

关键词：

D O I：

10.1109/DTIS.2006.1708651

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Among the attacks applied on secure circuits, fault injection techniques consist in the use of a combination of environmental conditions that induce computational errors in the chip that can leak protected informations. The purpose of our study is to build an accurate model able to describe the behaviour of CMOS circuits in presence of deliberated short supply voltage variations. This behaviour depends strongly on the basic gates (combinational logic, registers...) that make up the circuit. In this paper., we show why D-flip-flop are resistant to power supply glitches occurring between clock transitions and we propose an approach to evaluate the basic elements sensitivities towards faults generated by power glitches. Our aimed model Nvill consequently be dependent on this sensitivity.

引用

页码：257 / 261

页数：5

共 50 条

[31] Design of a Compact and Low Supply Voltage CMOS Voltage Reference Generator
Basyurt, Pinar Basak
Bonizzoni, Edoardo
Maloberti, Franco
Aksin, Devrim Yilmaz
23RD IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS CIRCUITS AND SYSTEMS (ICECS 2016), 2016, : 740 - 743
[32] Low Voltage CMOS Voltage-Controlled Multivibrator and Resonant VCO Circuits
Jasielski, Jacek
Kolodziejski, Wojciech
MIXDES 2009: PROCEEDINGS OF THE 16TH INTERNATIONAL CONFERENCE MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2009, : 302 - +
[33] Testing analog circuits by supply voltage variation and supply current monitoring
Kilic, Y
Zwolinski, M
PROCEEDINGS OF THE IEEE 1999 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 1999, : 155 - 158
[34] A LOW SUPPLY VOLTAGE HIGH PSRR VOLTAGE REFERENCE IN CMOS PROCESS
THAM, KM
NAGARAJ, K
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1995, 30 (05) : 586 - 590
[35] Supply current monitoring in CMOS circuits for reliability prediction and test
Richardson, A.M.
Dorey, A.P.
Quality and Reliability Engineering International, 1992, 8 (06) : 543 - 548
[36] Supply voltage strategies for minimizing the power of CMOS processors
Cai, J
Taur, Y
Huang, SF
Frank, DJ
Kosonocky, S
Dennard, RH
2002 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2002, : 102 - 103
[37] CMOS voltage buffer for extremely low supply operation
Univ of Technology and Agriculture, Bydgoszcz, Poland
Electron Technol (Warsaw), 3 (288-292):
[38] Supply and threshold voltage scaling for low power CMOS
Gonzalez, R
Gordon, BM
Horowitz, MA
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1997, 32 (08) : 1210 - 1216
[39] Minimum supply voltage for bulk Si CMOS GSI
Bhavnagarwala, AJ
Austin, B
Meindl, JD
1998 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN - PROCEEDINGS, 1998, : 100 - 102
[40] Low Voltage-Driven CMOS Circuits Based on SiOG
Choi, M. H.
Choi, J. W.
Park, S. H.
Choi, W. J.
Mativenga, M.
Jang, J.
Mruthyunjaya, R.
Tredwell, T. J.
Mozdy, E.
Williams, C. K.
ELECTROCHEMICAL AND SOLID STATE LETTERS, 2011, 14 (01) : J1 - J3

← 1 2 3 4 5 →