Interconnected magnetic tunnel junctions for spin-logic applications

被引:9
|
作者
Manfrini, Mauricio [1 ]
Vaysset, Adrien [1 ]
Wan, Danny [1 ]
Raymenants, Eline [1 ,2 ]
Swerts, Johan [1 ]
Rao, Siddharth [1 ]
Zografos, Odysseas [1 ,2 ]
Souriau, Laurent [1 ]
Gavan, Khashayar Babaei [1 ]
Rassoul, Nouredine [1 ]
Radisic, Dunja [1 ]
Cupak, Miroslav [1 ]
Dehan, Morin [1 ]
Sayan, Safak [3 ]
Nikonov, Dmitri E. [3 ]
Manipatruni, Sasikanth [3 ]
Young, Ian A. [3 ]
Mocuta, Dan [1 ]
Radu, Iuliana P. [1 ]
机构
[1] IMEC, Log Technol, B-3001 Leuven, Belgium
[2] Katholieke Univ Leuven, Dept Mat Engn, Leuven, Belgium
[3] Intel Corp, Components Res, Hillsboro, OR 97124 USA
关键词
INTEGRATED-CIRCUITS;
D O I
10.1063/1.5007622
中图分类号
TB3 [工程材料学];
学科分类号
0805 ; 080502 ;
摘要
With the rapid progress of spintronic devices, spin-logic concepts hold promises of energy-delay conscious computation for efficient logic gate operations. We report on the electrical characterization of domain walls in interconnected magnetic tunnel junctions. By means of spin-transfer torque effect, domains walls are produced at the common free layer and its propagation towards the output pillar sensed by tunneling magneto-resistance. Domain pinning conditions are studied quasi-statically showing a strong dependence on pillar size, ferromagnetic free layer width and inter-pillar distance. Addressing pinning conditions are detrimental for cascading and fan-out of domain walls across nodes, enabling the realization of domain-wallbased logic technology. (C) 2018 Author(s).
引用
收藏
页数:6
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