DVGen: Increasing coverage by automatically combining test specifications

被引：0
|
作者：
Rich, Kevin D. [1 ]
Shaw, Robert [1 ]
Govindaraju, Shankar G. [1 ]
Dobrikin, David [1 ]
机构：
[1] Transmeta Corp, Santa Clara, CA 95054 USA
来源：
HLDVT'06: ELEVENTH ANNUAL IEEE INTERNATIONAL HIGH-LEVEL DESIGN VALIDATION AND TEST WORKSHOP, PROCEEDINGS | 2006年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
DVGen is a novel microprocessor test generator that allows the verification engineer to focus only on capturing test intent via minimally constrained test specifications. DVGen combines test specifications to generate tests that preserve the intent of each specification while causing the concurrent occurrence of interesting events from each specification. DVGen is very effective at uncovering multi-dimensional corner case bugs, which have historically been the bane of complex designs.
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页码：3 / +
页数：2
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