Well-defined design procedure for a three-stage CMOS OTA

被引：4
|
作者：
Mita, R [1 ]
Palumbo, G [1 ]
Pennisi, S [1 ]
机构：
[1] Univ Catania, Dipartimento Ingn Elett Elettron & Sistemi, I-95125 Catania, Italy
来源：
2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS | 2005年
关键词：
D O I：
10.1109/ISCAS.2005.1465153
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A simple and well-defined design procedure for a three-stage CMOS OTA is presented in this paper. The approach is suited for a pencil-and-paper design and yields accurate performance optimization without introducing unnecessary circuit constraints. Simulations on a circuit implemented in a 0.35-mu m technology closely agree the results expected.
引用
收藏
页码：2579 / 2582
页数：4
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