Analysis of the impact of reticle CD variations on the available process windows for a 100nm CMOS process

With the decreasing gate length and pitch, line-width variations on the mask become more and more important. In low k1 imaging situations often a high Mask Error Enhancement Factor (MEEF) is present and optical proximity correction (OPC) is used to correct for printed CD variation through pitch. In such situations it is often not clear what the impact of reticle line-width variations is on the performance of the litho process and what the interaction is with other process variations present in the litho process. In this manuscript a method will be explained to derive the impact of the reticle CD deviations on the process windows for low k1 imaging. This method will allow varying the various reticle specifications: the CD mean-to-target and uniformity, the writing grid size and the pitch proximity effect during reticle fabrication. By varying these input parameters and looking at the corresponding process window reductions a more founded decision can de made about the specification for these parameters when ordering reticles. After explaining the method also a reality check will be done for a 100nm CMOS process with a modem 193nm resist on a high NA (63 and 0.75) ArF scanner.