Design method for high reliable flip chip EGA package

被引：0
|
作者：
Saito, N [1 ]
Yamada, O [1 ]
Ono, T [1 ]
Uda, T [1 ]
机构：
[1] Hitachi Ltd, Mech Engn Lab, Tsuchiura, Ibaraki 3000013, Japan
来源：
51ST ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE | 2001年
关键词：
D O I：
暂无
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
An efficient design method for flip chip ball grid array (BGA) packages has been developed. This method uses design of experiment (DOE), a series of finite element (FE) stress analyses based on an orthogonal array used in DOE, and statistical analysis. By using this method to design a EGA package having 1600 pins, the warpage of the optimum packaging structure is very small and all of the reliability demands are satisfied.
引用
收藏
页码：270 / 275
页数：6
相关论文
共 50 条
  • [31] Thermal performance of a high end flip-chip organic package
    Calmidi, VV
    Sathe, SB
    2003 INTERNATIONAL SYMPOSIUM ON MICROELECTRONICS, 2003, 5288 : 511 - 516
  • [32] Thinner Package Process for High Band Width Flip Chip CSP
    Chen, Han Hung
    Chen, Yu Kai
    Hsiao, Wen Hung
    Wang, Yu Sheng
    Lin, Rong Zheng
    Hsu, Yuan-Hung
    Lin, Chang Fu
    2018 13TH INTERNATIONAL MICROSYSTEMS, PACKAGING, ASSEMBLY AND CIRCUITS TECHNOLOGY CONFERENCE (IMPACT), 2018, : 234 - 236
  • [33] Development of a new improved high performance flip chip BGA package
    Chong, DYR
    Lim, BK
    Rebibis, KJ
    Pan, SJ
    Krishnamoorthi, S
    Kapoor, R
    Sun, AYS
    Tan, HB
    54TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, VOLS 1 AND 2, PROCEEDINGS, 2004, : 1174 - 1180
  • [34] Development of thermal solution for high power flip chip CPU package
    Kwon, HK
    Lee, TK
    Baek, JH
    Chun, JW
    Kim, MH
    Po, YH
    Oh, SY
    2000 HD INTERNATIONAL CONFERENCE ON HIGH-DENSITY INTERCONNECT AND SYSTEMS PACKAGING, 2000, 4217 : 313 - 319
  • [35] Electronics packaging technology update: EGA, CSP, DCA, and flip chip
    Lau, JH
    1ST 1997 IEMT/IMC SYMPOSIUM, 1997, : 32 - 36
  • [36] Thin Profile Flip Chip Package-on-Package Development
    Hsieh, Ming-Che
    Kang, KeonTaek
    Choi, HangChul
    Kim, YoungCheol
    2016 11TH INTERNATIONAL MICROSYSTEMS, PACKAGING, ASSEMBLY AND CIRCUITS TECHNOLOGY CONFERENCE (IMPACT-IAAC 2016), 2016, : 143 - 147
  • [37] Development of thin flip-chip BGA for package on package
    Suzuki, Yasuhiro
    Kayashima, Yuuji
    Maeda, Takehik
    Matsuura, Yoshihiro
    Sekiguchi, Tomobisa
    Watanabe, Akio
    57TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2007 PROCEEDINGS, 2007, : 8 - +
  • [38] Advanced Flip Chip Package on Package Technology for Mobile Applications
    Hsieh, Ming-Che
    2016 17TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY (ICEPT), 2016, : 486 - 491
  • [39] Package characterization and development of a flip chip QFN package: fcMLF
    McCann, DR
    Ha, SH
    52ND ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2002 PROCEEDINGS, 2002, : 365 - 371
  • [40] AN EFFICIENT BUMP PAD DESIGN TO MITIGATE THE FLIP CHIP PACKAGE INDUCED STRESS
    Gonzalez, Mario
    De Vos, Joeri
    Van der Plas, Geert
    Beyne, Eric
    INTERNATIONAL TECHNICAL CONFERENCE AND EXHIBITION ON PACKAGING AND INTEGRATION OF ELECTRONIC AND PHOTONIC MICROSYSTEMS, 2015, VOL 2, 2015,
12345