Effect of Temperature on Performance of 5-nm Node Silicon Nanosheet Transistors for Analog Applications

被引:6
|
作者
Pundir, Yogendra Pratap [1 ,2 ]
Bisht, Arvind [1 ]
Saha, Rajesh [1 ]
Pal, Pankaj Kumar [1 ]
机构
[1] Natl Inst Technol Uttarakhand, Uttarakhand 246174, India
[2] Hemvati Nandan Bahuguna Garhwal Univ, Uttarakhand 246174, India
关键词
Analog Performance; Gain frequency product; Intrinsic gain; Nanosheet Transistor; Unit gain frequency;
D O I
10.1007/s12633-022-01800-w
中图分类号
O64 [物理化学(理论化学)、化学物理学];
学科分类号
070304 ; 081704 ;
摘要
This work investigates the effects of temperature on the performance of a 5-nm node N-channel Nanosheet Transistor (NST) for analog applications. A fully calibrated commercial TCAD platform is used for the device as well as mixed-mode circuit simulations. The range of temperature used in the study is from 250 to 450 K. The transconductance (g(m)) of the NST shows a change in the sign of its temperature coefficient (TC), from positive to negative, around a gate voltage of 0.52 V. The Output-conductance (g(ds)) and Early-voltage (V-EA) parameters increase with the increase in temperature. However, the Intrinsic-gain (A(v)), Transconductance-generation-efficiency (g(m)/I-DS), Unit-gain-frequency (f(T)), Gain-Frequency product (GFP), Transconductance-Frequency product (TFP), and Gain- Transconductance-Frequency product (GTFP) parameters are observed to deteriorate with the increasing temperature. For the increase in temperature from 250 to 450 K: the maximum g(m) value is seen to decrease from 228 mu S to 200 mu S; the g(ds) values increase from 24.6 mu S to 27.1 mu S; the early voltage (at V-GS = 400 mV) improves from 2.37 to 2.71 V; the f(T) value decreases from 568 GHz to 524 GHz; the A(v) value falls from 9.2 to 7.4; Discharge-time (t(d)) value improves from 9.45 ns to 8.11 ns; the g(m)/I-DS values degrade from 37.5 V- 1 to 22.4 V- 1; the GFP value falls from 5.22 THz to 3.86 THz.
引用
收藏
页码:10581 / 10589
页数:9
相关论文
共 50 条
  • [1] Effect of Temperature on Performance of 5-nm Node Silicon Nanosheet Transistors for Analog Applications
    Yogendra Pratap Pundir
    Arvind Bisht
    Rajesh Saha
    Pankaj Kumar Pal
    Silicon, 2022, 14 : 10581 - 10589
  • [2] Design Insights of Nanosheet FET and CMOS Circuit Applications at 5-nm Technology Node
    Sreenivasulu, V. Bharath
    Narendar, Vadthiya
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2022, 69 (08) : 4115 - 4122
  • [3] Threshold Voltage Variations Induced by Si1-xGex and Si1-xCx of Sub 5-nm Node Silicon Nanosheet Field-Effect Transistors
    Jeong, Jinsu
    Yoon, Jun-Sik
    Lee, Seunghwan
    Baek, Rock-Hyun
    JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, 2020, 20 (08) : 4684 - 4689
  • [4] A Comparative Review: Performance parameters of Fin, Nanowire and Nanosheet Field Effect Transistors on 5nm node
    Karutharaja, V.
    Balamurugan, N. B.
    Suguna, M.
    Kumar, D. Sriram
    2024 7TH INTERNATIONAL CONFERENCE ON DEVICES, CIRCUITS AND SYSTEMS, ICDCS 2024, 2024, : 308 - 312
  • [5] Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub 5-nm Node SoC Application
    Jeong, Jinsu
    Yoon, Jun-Sik
    Lee, Seunghwan
    Baek, Rock-Hyun
    IEEE ACCESS, 2020, 8 : 35873 - 35881
  • [6] Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications
    Yoon, Jun-Sik
    Baek, Rock-Hyun
    IEEE ACCESS, 2020, 8 (08): : 189395 - 189403
  • [7] Effect of fin shape of tapered FinFETs on the device performance in 5-nm node CMOS technology
    Kurniawan, Erry Dwi
    Yang, Hao
    Lin, Chia-Chou
    Wu, Yung-Chun
    MICROELECTRONICS RELIABILITY, 2018, 83 : 254 - 259
  • [8] Prediction of Alpha Particle Effect on 5-nm Vertical Field-Effect Transistors
    Seo, Youngsoo
    Kang, Myounggon
    Jeon, Jongwook
    Shin, Hyungcheol
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2019, 66 (01) : 806 - 809
  • [9] Simulation Study of Vertically Stacked Lateral Si Nanowires Transistors for 5-nm CMOS Applications
    Al-Ameri, Talib
    Georgiev, Vihar P.
    Adamu-Lema, Fikru
    Asenov, Asen
    IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2017, 5 (06): : 466 - 472
  • [10] Effect of gate length on performance of 5nm node N-channel nano-sheet transistors for analog circuits
    Pundir, Yogendra Pratap
    Saha, Rajesh
    Pal, Pankaj Kumar
    SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2021, 36 (01)