Heterogeneous 3-D Integration of Multitier Compute-in-Memory Accelerators: An Electrical-Thermal Co-Design

Emerging nonvolatile memory (eNVM)-based compute-in-memory (CIM) accelerators have been proven in silicon for machine learning at the macrolevel. To fully unleash the system-level benefits, the heterogeneous 3-D integration (H3D) using through-silicon via (TSV) is a promising approach, to: 1) address the challenges of areahungry peripheries in CIM accelerators; 2) solve the 2-D scaling challenges of eNVM; and 3) stack enormous amount of embedded memories that are required in state-of-theart deep neural network models. This article presents an electrical-thermal co-design of multitier CIM accelerators, based on SRAMand/oreNVM, with hybrid technology nodes for logic andmemory tiers. We benchmark the CIMaccelerators on 8-bit ResNet-34 for ImageNet recognition, with layerby-layer and pipelined schemes, respectively. By sweeping TSV diameter from 30 mu m to 100 nm, we investigate the tradeoffs of system performance metrics (TOPS/W, TOPS, and TOPS/mm(2)) and H3D challenges (thermal and IR-drop in power delivery). Finally, we find the sweet spot of TSV diameter for multitier H3D system is 1-3 mu m, to guarantee balanced area-overhead, performance, and IR-drop in power delivery. The extended benchmark framework is released onGitHub ( https:// github. com/ neurosim) as an open-source tool for the research community.