Cryogenic Transport Characteristics of P-Type Gate-All-Around Silicon Nanowire MOSFETs

被引:17
|
作者
Gu, Jie [1 ,2 ]
Zhang, Qingzhu [1 ]
Wu, Zhenhua [1 ,2 ]
Yao, Jiaxin [1 ,2 ]
Zhang, Zhaohao [1 ]
Zhu, Xiaohui [1 ,2 ]
Wang, Guilei [1 ]
Li, Junjie [1 ,2 ]
Zhang, Yongkui [1 ]
Cai, Yuwei [1 ,2 ]
Xu, Renren [1 ,2 ]
Xu, Gaobo [1 ,2 ]
Xu, Qiuxia [1 ]
Yin, Huaxiang [1 ,2 ]
Luo, Jun [1 ,2 ]
Wang, Wenwu [1 ,2 ]
Ye, Tianchun [1 ,2 ]
机构
[1] Chinese Acad Sci, Inst Microelect, Key Lab Microelect Devices & Integrated Technol, Beijing 100029, Peoples R China
[2] Univ Chinese Acad Sci, Sch Elect Elect & Commun Engn, Beijing 100049, Peoples R China
关键词
gate-all-around; Si nanowire; cryo-CMOS; one-dimensional hole transport;
D O I
10.3390/nano11020309
中图分类号
O6 [化学];
学科分类号
0703 ;
摘要
A 16-nm-L-g p-type Gate-all-around (GAA) silicon nanowire (Si NW) metal oxide semiconductor field effect transistor (MOSFET) was fabricated based on the mainstream bulk fin field-effect transistor (FinFET) technology. The temperature dependence of electrical characteristics for normal MOSFET as well as the quantum transport at cryogenic has been investigated systematically. We demonstrate a good gate-control ability and body effect immunity at cryogenic for the GAA Si NW MOSFETs and observe the transport of two-fold degenerate hole sub-bands in the nanowire (110) channel direction sub-band structure experimentally. In addition, the pronounced ballistic transport characteristics were demonstrated in the GAA Si NW MOSFET. Due to the existence of spacers for the typical MOSFET, the quantum interference was also successfully achieved at lower bias.
引用
收藏
页码:1 / 11
页数:11
相关论文
共 50 条
  • [21] Simulation of flicker noise in gate-all-around Silicon Nanowire MOSFETs including interface traps
    Anandan, P.
    Nithya, A.
    Mohankumar, N.
    MICROELECTRONICS RELIABILITY, 2014, 54 (12) : 2723 - 2727
  • [22] 6-T SRAM Cell Design with Gate-All-Around Silicon Nanowire MOSFETs
    Liao, Yi-Bo
    Chiang, Meng-Hsueh
    Damrongplasit, Nattapol
    Liu, Tsu-Jae King
    Hsu, Wei-Chou
    2013 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS (VLSI-TSA), 2013,
  • [23] Self-Heating Effects in Gate-all-around Silicon Nanowire MOSFETs: Modeling and Analysis
    Huang, Xin
    Zhang, Tianwei
    Wang, Rusheng
    Liu, Changze
    Liu, Yuchao
    Huang, Ru
    2012 13TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED), 2012, : 727 - 731
  • [24] Hot carrier and PBTI induced degradation in silicon nanowire gate-all-around SONOS MOSFETs
    Choi, Jin Hyung
    Han, Jin-Woo
    Yu, Chong Gun
    Park, Jong Tae
    MICROELECTRONICS RELIABILITY, 2014, 54 (9-10) : 2325 - 2328
  • [25] Dopant-Segregated Schottky Silicon-Nanowire MOSFETs With Gate-All-Around Channels
    Chin, Yoke King
    Pey, Kin-Leong
    Singh, Navab
    Lo, Guo-Qiang
    Tan, Khing Hong
    Ong, Chio-Yin
    Tan, L. H.
    IEEE ELECTRON DEVICE LETTERS, 2009, 30 (08) : 843 - 845
  • [26] Design and optimization considerations for bulk gate-all-around nanowire MOSFETs
    Song, Yi
    Xu, Qiuxia
    Zhou, Huajie
    Cai, Xiaowu
    SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2009, 24 (10)
  • [27] Performance and Variability Studies of InGaAs Gate-all-Around Nanowire MOSFETs
    Conrad, Nathan
    Shin, SangHong
    Gu, Jiangjiang
    Si, Mengwei
    Wu, Heng
    Masuduzzaman, Muhammad
    Alam, Mohammad A.
    Ye, Peide D.
    IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2013, 13 (04) : 489 - 496
  • [28] Low-temperature (cryogenic) Transport in Gate-All-Around (GAA) Silicon Nanowire Field-Effect Transistor
    Verma, Amit
    Nekovei, Reza
    Shiri, Daryoush
    2024 IEEE 24TH INTERNATIONAL CONFERENCE ON NANOTECHNOLOGY, NANO 2024, 2024, : 122 - 125
  • [29] Design study of the gate-all-around silicon nanosheet MOSFETs
    Lee, Yongwoo
    Park, Geon-Hwi
    Choi, Bongsik
    Yoon, Jinsu
    Kim, Hyo-Jin
    Kim, Dae Hwan
    Kim, Dong Myong
    Kang, Min-Ho
    Choi, Sung-Jin
    SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2020, 35 (03)
  • [30] 3-D Modeling of Fringing Gate Capacitance in Gate-all-around Cylindrical Silicon Nanowire MOSFETs
    An, TaeYoon
    Kim, SoYoung
    2013 18TH INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES (SISPAD 2013), 2013, : 256 - 259