Modeling of CGRA to Improve Power Efficiency for Computationally Intensive Application

被引:0
|
作者
Tehre, Vaishali [1 ]
Agrawal, Pankaj [2 ]
Kshirsagar, R. V. [3 ]
Dorle, S. S. [1 ]
机构
[1] GHRCE, Nagpur, Maharashtra, India
[2] RCOEM, Nagpur, Maharashtra, India
[3] PCE, Nagpur, Maharashtra, India
来源
2013 SIXTH INTERNATIONAL CONFERENCE ON EMERGING TRENDS IN ENGINEERING AND TECHNOLOGY (ICETET 2013) | 2013年
关键词
CGRA; processing element; FPGA; ASIC;
D O I
10.1109/ICETET.2013.71
中图分类号
TP39 [计算机的应用];
学科分类号
081203 ; 0835 ;
摘要
To achieve high computational efficiency by maintaining low power and area requirement is becoming vitally important task for many computationally intensive applications in mobile devices. Designing an architecture for such complex application on ASIC is the traditional method which gives good performance by sacrificing flexibility. The many researchers are trying to achieve both performance and flexibility by exploring CGRA architecture which is a alternative of FPGA. This paper present a coarse grained architecture model for implementing low power complex application.
引用
收藏
页码:123 / 125
页数:3
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