Power analysis of high throughput pipelined carry-propagation adders

In several previous papers the area, delay, and power consumption for various carry-propagation adders have been compared. However for high throughput applications it may be necessary to introduce pipelining into the adder The number of stages to be inserted and the width of the pipelining registers differs between different adders structure. In this work we focus on the power consumption for adder structures when pipelining is used to increase the throughput. Four. adder structures with varying wordlengths and pipeline levels are implemented using standard cells and the power consumption is compared. The results show that the Kogge-Slone parallel prefix adder gives the lowest power consumption given the throughput most of the time.