Design of a configurable embedded processor architecture for DSP functions

被引：0
|
作者：
Yue, H [1 ]
Lai, MC [1 ]
Dai, K [1 ]
Wang, ZY [1 ]
机构：
[1] Natl Univ Def Technol, Sch Comp, Changsha 410073, Hunan, Peoples R China
来源：
11TH INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED SYSTEMS WORKSHOPS, VOL II, PROCEEDINGS, | 2005年
关键词：
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
Most of the embedded applications are served today by general-purpose processors or special-purpose ASIC processors containing hundreds to thousands of ALUs. While such solutions are efficient, they lack flexibility and are not feasible for certain embedded applications. ASIP(Application Specific Instruction Processor) design methodology can not only satisfy the functionality and performance requirements of the embedded systems but also flexible. So it is widely adopted in embedded processor design domain. For the widely adopting of digital signal processing in the embedded applications, this paper studies a configurable VLIW processor architecture based oil TTA(Transport Triggered Architecture) for high performance digital signal processing in embedded systems. The methodology of ASIP design is applied and some handle optimizations are taken. It is shown that it has high performance to run the digital signal processing kernel applications, and its simplicity and flexibility encourages for further development with tuned functionality.
引用
收藏
页码：27 / 31
页数：5
相关论文
共 50 条
  • [1] Embedded tools for a configurable and customizable DSP architecture
    Liem, C
    Breant, F
    Jadhav, S
    O'Farrell, R
    Ryan, R
    Levia, O
    IEEE DESIGN & TEST OF COMPUTERS, 2002, 19 (06): : 27 - 35
  • [2] Design on Embedded Processor with Configurable Divider
    Zhang, Song
    Zhang, Yi
    Ba, Lianfa
    Li, Wenjiang
    INDUSTRIAL INSTRUMENTATION AND CONTROL SYSTEMS II, PTS 1-3, 2013, 336-338 : 1504 - +
  • [3] Design methodology and system for a configurable media embedded processor extensible to VLIW architecture
    Mizuno, A
    Kohno, K
    Ohyama, R
    Tokuyoshi, T
    Uetani, H
    Eichel, H
    Miyamori, T
    Matsumoto, N
    Matsui, M
    ICCD'2002: IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, 2002, : 2 - 7
  • [4] An embedded-processor architecture for parallel DSP algorithms
    Hobson, RF
    Wong, PS
    Evenson, SA
    ADVANCED SIGNAL PROCESSING ALGORITHMS, ARCHITECTURES, AND IMPLEMENTATIONS VI, 1996, 2846 : 75 - 85
  • [5] Configurable multi-processor architecture and its processor element design
    Nishimura, Tsutomu
    Miki, Takuji
    Sugiura, Hiroaki
    Matsumoto, Yuki
    Kobayashi, Masatsugu
    Kato, Toshiyuki
    Eda, Tsutomu
    Yamauchi, Hironori
    ASP-DAC 2006: 11TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, PROCEEDINGS, 2006, : 124 - +
  • [6] Application specific processor design for H.264 decoder with a configurable embedded processor
    Han, JH
    Lee, MY
    Bae, Y
    Cho, HJ
    ETRI JOURNAL, 2005, 27 (05) : 491 - 496
  • [7] Software Cache Support and API Design for Embedded DSP Processor
    Lin, Cheng-Yen
    Wang, Shao-Chung
    Hung, Ming-Yu
    Hsieh, Kun-Yuan
    Lee, Jenq Kuen
    2009 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2009), 2009, : 161 - 164
  • [8] A software-configurable processor architecture
    Gonzalez, Ricardo E.
    IEEE MICRO, 2006, 26 (05) : 42 - 51
  • [9] Configurable MBIST Processor for Embedded Memories Testing
    Wojciechowski, Andrzej A.
    Marcinek, Krzysztof
    Pleskacz, Witold A.
    PROCEEDINGS OF THE 2019 26TH INTERNATIONAL CONFERENCE MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS (MIXDES 2019), 2019, : 341 - 344
  • [10] MPEG-4 video codec IP design with a configurable embedded processor
    Kim, JG
    Kuo, CCJ
    PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II: COMMUNICATIONS-MULTIMEDIA SYSTEMS & APPLICATIONS, 2003, : 776 - 779
12345