A low-voltage low-noise digital buffer system

被引：0
|
作者：
Secareanu, RM [1 ]
Peterson, B [1 ]
Hartman, D [1 ]
机构：
[1] Motorola Inc, Semicond Prod Sector, Digital DNA Labs, Tempe, AZ 85284 USA
来源：
2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL IV, PROCEEDINGS | 2002年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A novel low-voltage CMOS digital buffer is proposed. The primary characteristic of this digital buffer is the low voltage operation (V-DD between one and two transistor threshold voltages (V(T)s), with a typical V-DD = 1.5V(T)). While operating at this reduced power supply, low noise and high overall performances are achieved.
引用
收藏
页码：181 / 184
页数：4
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