A Layout-Based Rad-Hard DICE Flip-Flop Design

被引：10

作者：

Wang, Haibin ^{[1
,2
,3
]}

Dai, Xixi ^{[1
]}

Ibrahim, Younis Mohammed Younis ^{[1
]}

Sun, Hongwen ^{[1
]}

Nofal, Issam ^{[4
]}

Cai, Li ^{[3
]}

Guo, Gang ^{[3
]}

Shen, Zicai ^{[5
]}

Chen, Li ^{[2
]}

机构：

[1] Hohai Univ, Coll IoT Engn, Changzhou 213022, Peoples R China

[2] Univ Saskatchewan, Coll Engn, Saskatoon S7N 5A9, SK, Canada

[3] China Inst Atom Energy, Innovat Fdn Radiat Applicat, Beijing 102413, Peoples R China

[4] iRoC Technol, F-38000 Grenoble, France

[5] Beijing Inst Spacecraft Environm Engn, Beijing 100094, Peoples R China

来源：

JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS | 2019年 / 35卷 / 01期

关键词：

DICE; LEAP DICE; Rad-hard flip-flop; Single event upset; Charge sharing; SINGLE-EVENT UPSET; CHARGE COLLECTION; 130; NM; MITIGATION;

D O I：

10.1007/s10836-019-05773-4

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The DICE flip-flop has been rendered ineffective in deep-submicron technology nodes (e.g. 65nm and 28nm) due to charge sharing when exposed to single event strikes. This paper presents a new single event upset tolerant flip-flop design by applying the hardening technique on DICE at the layout level. This approach is an alternative to existing Layout Design through Error-Aware Transistor Positioning (LEAP); it also re-places transistors in master and slave DICE latches in the zigzag fashion in the layout. Both computer simulations and heavy-ion experimental results demonstrate that our proposed layout design has no single event upset errors under normal strikes until LET=37MeVcm(2)/mg compared to the traditional DICE structure.

引用

页码：111 / 117

页数：7

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