A Layout-Based Rad-Hard DICE Flip-Flop Design

The DICE flip-flop has been rendered ineffective in deep-submicron technology nodes (e.g. 65nm and 28nm) due to charge sharing when exposed to single event strikes. This paper presents a new single event upset tolerant flip-flop design by applying the hardening technique on DICE at the layout level. This approach is an alternative to existing Layout Design through Error-Aware Transistor Positioning (LEAP); it also re-places transistors in master and slave DICE latches in the zigzag fashion in the layout. Both computer simulations and heavy-ion experimental results demonstrate that our proposed layout design has no single event upset errors under normal strikes until LET=37MeVcm(2)/mg compared to the traditional DICE structure.